There are a number of integrated circuit memories commercially available. For example, dynamic memory circuits having memory cells arranged to be accessed in a random fashion are referred to as dynamic random access memories, DRAMs. These memories can be produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells. One such method is page mode operations. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell array and randomly accessing different columns of the array. Data stored at the row and column intersection can be output while that column is accessed. An alternate type of memory access is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. Yet another type of operation is included in a burst EDO memory which adds the ability to address one column of a memory array and then automatically address additional columns in a pre-determined manner without providing the additional column addresses on external address lines. A more detailed description of a DRAM having EDO features is provided in the "1995 DRAM Data Book" pages 1-1 to 1-30 available from Micron Technology, Inc. Boise, Id., the assignee of the present application and is incorporated herein by reference.
DRAMs typically have bi-directional data lines which operate as both data inputs and data outputs. Data is written to the memory circuit using either a strobe signal or a clock. The output of a typical DRAM, however, is not strobed or clocked such that an external system reading the DRAM will not know when valid data is available from the DRAM. That is, an external system reading a DRAM must delay reading the data lines until it is known that valid data is present on the data lines before reading the memory. A time delay is incorporated therefore, after the data read request is signaled to the memory to ensure the reading of valid data from the memory circuit. This time delay may be longer than needed and as a result slows the external system down.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory circuit which provides a signal that indicates when valid data is available on the output data lines.